adg728/ADG729 a rev. prc august 99 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1999 cmos, low voltage, 2 wire, serially controlled matrix switches preliminary technical data preliminary technical data features two wire serial interface +2.7 v to +5.5 v single supply low on resistance (4 w w w w w ) low on resistance flatness low leakage single 8 to 1 matrix switch adg728 dual 4 to 1 matrix switch ADG729 power on reset fast switching times low power consumption applications data acquisition systems communication systems relay replacement audio and video switching general description the adg728 and ADG729 are cmos analog matrix switches with a serially controlled two wire interface. the adg728 is an 8 channel matrix switch, while the ADG729 is a dual 4 channel matrix switches. on resistance is closely matched between switches and very flat over the full signal range. these parts can operate equally well as either multiplexers, de-multiplexers or switch arrays and the input signal range extends to the supplies. the adg728 and ADG729 utilize a two wire serial interface that is compatible with the i 2 c tm interface standard. both have two external address pins (a0 and a1). this allows the 2 lsbs of the 7-bit slave address to be set by the user. four of each devices can be connected to the one bus. the adg728 also has a reset pin, this should be tied high if not in use. each channel is controlled by one bit of an 8 bit word. this means that these devices may be used in a number of different configurations, all, any or none of the channels may be on at any one time. product highlights 1. two wire serial interface. 2. single supply operation. the adg728 and ADG729 are fully specified and guaranteed with +3 v and +5 v supply rails. 3. low r on (4 w ). 4. any configuration of switches may be on at any one time. 5. break before make switching action. 6. small 16 lead tssop package. functional block diagrams i 2 c is a trademark of philips corporation. s1 s8 sda d scl a0 input register adg728 s1a sda da scl s4a s1b s4b db a0 ADG729 a1 input register a1 reset on power up of the device, all switches will be in the off condition and the internal shift register will contain all zeros. all channels exhibit break before make switching action preventing momentary shorting when switching channels. the adg728 and ADG729 are available in a 16 lead tssop package.
C2C rev. prc adg728/ADG729Cspecifications 1 (v dd = +5 v 10%, gnd = 0 v) preliminary technical data b version C40c parameter +25 o c to +85c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on ) 2.5 w typ v s = 0 v to v dd , i s = 10 ma; 4 4.5 w max test circuit 1; on-resistance match between 0.1 w typ channels ( d r on ) 0.4 w max v s = 0 v to v dd , i s = 10 ma; on-resistance flatness (r flat(on) ) 0.75 w typ v s = 0 v to v dd , i s = 10 ma; 1.2 w max leakage currents source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2; drain off leakage i d (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2; channel on leakage i d , i s (on) 0.01 na typ v d = v s = 1 v, or 4.5v; 0.1 0.3 na max test circuit 3; logic inputs (a0, a1) 2 input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ 0.1 a max cin, input capacitance 3 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7v dd v min v dd +0.3 vmax input low voltage, v inl -0.3 v min 0.3v dd v max i in , input leakage current t b d m a typ v in = 0v to v dd . tbd m a max v hyst , input hysteresis 0.05v dd v min c in , input capacitance 3 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on 30 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 3 v, test circuit 4; t off 21 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 3 v, test circuit 4; break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf 1 ns min v s1 = v s2 = 3 v, test circuit 5 charge injection 5 pc typ v s = 2 v, r s = 0 w , c l = 1 nf; test circuit 5; off isolation -60 db typ r l = 50 w , c l = 5 pf, f = 10mhz; test circuit 6; crosstalk -80 db typ r l = 50 w , c l = 5 pf, f = 10mhz; test circuit 7; -3 db bandwidth 200 mhz typ r l = 50 w , c l = 5 pf, test circuit 6; c s (off) tbd pf typ c d (off) tbd pf typ c d , c s (on) t b d pf typ power requirements v dd = +5.5 v i dd 10 a typ digital inputs = 0 v or 5.5 v tbd a max notes 1 temperature range is as follows: b version: C40c to +85c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
C3C rev. prc preliminary technical data adg728/ADG729Cspecifications 1 (v dd = +5 v 10%, gnd = 0 v) C40c parameter +25 o c to +85c units test conditions/comments analog switch analog signal range 0 v to v dd v on-resistance (r on ) 4.5 5 w typ v s = 0 v to v dd , i s = 10 ma; 8 w max test circuit 1; on-resistance match between 0.1 w typ v s = 0 v to v dd , i s = 10 ma; channels ( d r on ) 0.4 w max v s = 0 v to v dd , i s = 10 ma; on-resistance flatness (r flat(on) ) 2.5 w max leakage currents v dd = +3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.3 na max test circuit 2; drain off leakage i d (off) 0.01 na typ v s = 1 v/3 v, v d = 3 v/1 v; 0.1 0.3 na max test circuit 2; channel on leakage i d , i s (on) 0.01 na typ v s = v d = +1 v or +3 v; 0.1 0.3 na max test circuit 3; logic inputs (a0, a1) 2 input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.005 a typ 0.1 a max cin, input capacitance 3 pf typ logic inputs (scl, sda) 2 input high voltage, v inh 0.7v dd v min v dd +0.3 vmax input low voltage, v inl -0.3 v min 0.3v dd v max i in , input leakage current t b d m a typ v in = 0v to v dd . tbd m a max v hyst , input hysteresis 0.05v dd v min c in , input capacitance 3 pf typ logic output (sda) 2 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma dynamic characteristics 2 t on 35 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 2 v, test circuit 4; t off 27 ns typ r l = 300 w , c l = 35 pf; t b d ns max v s = 2 v, test circuit 4; break-before-make time delay, t d 15 ns typ r l = 300 w , c l = 35 pf 1 ns min v s1 = v s2 = 2 v, test circuit 5 charge injection 5 pc typ v s = 1.5 v, r s = 0 w , c l = 1 nf; test circuit 5; off isolation -60 db typ r l = 50 w , c l = 5 pf, f = 10 mhz; test circuit 6; crosstalk -80 db typ r l = 50 w , c l = 5 pf, f = 10mhz; test circuit 7; -3 db bandwidth 200 mhz typ r l = 50 w , c l = 5 pf, test circuit 6; c s (off) tbd pf typ c d (off) tbd pf typ c d , c s (on) t b d pf typ power requirements v dd = +3.3 v i dd 10 a typ digital inputs = 0 v or 3.3 v tbd a max notes 1 temperature ranges are as follows: b versions: C40c to +85c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice.
C4C rev. prc preliminary technical data preliminary technical data adg728/ADG729 timing characteristics 1 parameter limit at t min , t max units conditions/comments fscl 400 khz max scl clock frequency t 1 2.5 m s min scl cycle time t 2 0.6 m s min t high , scl high time t 3 1.3 m s min t low , scl low time t 4 0.6 m s min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 2 0.9 m s max t hd, dat , data hold time 0 m s min t 7 0.6 m s min t su, sta , setup time for repeated start t 8 0.6 m s min t su, sto , stop condition setup time t 9 1.3 m s min t buf , bus free time between a stop condition and a start condition t 10 300 ns max t r , rise time of both scl and sda when receiving 20 + 0.1c b 3 ns min t 11 250 ns max t f , fall time of sda when receiving 300 ns max t f , fall time of both scl and sda when transmitting 20 + 0.1c b 3 ns min c b 400 pf max capacitive load for each bus line t sp 4 50 ns max pulse width of spike suppressed notes 1 see figure 1. 2 a master device must provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 3 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3v dd and 0.7v dd . 4 input filtering on both the scl and sda inputs suppress noise spikes which are less than 50ns. specifications subject to change without notice. figure 1. 2-wire serial interface timing diagram. t 9 t 4 t 6 t 5 t 7 t 8 t 1 t 2 t 4 t 11 t 10 t 3 start condition repeated start condition stop condition sda scl (v dd = +2.5 v to +5.5 v . all specifications C40c to +85cunless otherwise noted)
adg728/ADG729 C5C rev. prc preliminary technical data preliminary technical data pin configurations ordering guide model temperature range package description package option adg728bru -40 o c to +85 o c thin shrink small outline package (tssop) ru-16 ADG729bru -40 o c to +85 o c thin shrink small outline package (tssop) ru-16 scl reset s2 s3 s4 s1 d 1 2 16 15 5 6 7 12 11 10 3 4 14 13 8 9 top view (not to scale) adg728 a0 a1 s5 s6 s7 gnd v dd s8 sda scl a1 sda a0 gnd s2a s3a s4a s2b s3b s4b s1a v dd s1b da db 1 2 16 15 5 6 7 12 11 10 3 4 14 13 89 top view (not to scale) ADG729 ADG729 pin function description adg728 ADG729 mnemonic function 1 1 s c l serial clock line. this is used in conjunction with the sda line to clock data into the 16-bit input shift register. clock rates of up to 400kbit/s can be accommodated with this 2-wire serial interface. 2- reset active low control input that clears the input register and turns all switches to the off condition. 3 3 s d a serial data line. this is used in conjunction with the scl line to clock data into the 8-bit input shift register during the write cycle and used to read back 1 byte of data during the read cyle. it is a bidirectional open-drain data line which should be pulled to the supply with an external pull-up resistor. 4,5,6,7 4,5,6,7 sxx source. may be an input or output. 8 8,9 d x drain. may be an input or output. 9,10,11,12 10,11,12,13 s x x source. may be an input or output. 13 14 v dd power supply input. these parts can be operated from a supply of +2.5v to +5.5v. 14 15 gnd ground reference. 15 2 a1 address input. sets the 2nd least significant bit of the 7 bit slave address. 16 16 a0 address input. sets the least significant bit of the 7 bit slave address. adg728
C6C rev. prc preliminary technical data preliminary technical data adg728/ADG729 r on ohmic resistance between d and s. r flat(on) flatness is defined as the difference between the maximum and minimum value of on- resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d ,c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. see test circuit 4. terminology t off delay between applying the digital control input and the output switching off. off isolation a measure of unwanted signal coupling through an off switch. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by -3dbs. on response the frequency response of the on switch. on loss the voltage drop across the on switch seen on the on response vs. frequency plot as how many dbs the signal is away from 0db. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd C0.3 v to +7 v analog, digital inputs 2 -0.3v to v dd +0.3 v or 30 ma, whichever occurs first peak current, s or d 100ma (pulsed at 1 ms, 10% duty cycle max) continuous current, each s 30ma continuous current d, ADG729 80ma continuous current d, adg728 120ma operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature +150c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg728/ADG729 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. tssop package, power dissipation mw q ja thermal impedance 150.4c/w q jc thermal impedance 27.6c/w lead temperature, soldering vapor phase (60 sec) +215c infrared (15 sec) +220c esd tbdkv notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at in, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given.
adg728/ADG729 C7C rev. prc preliminary technical data preliminary technical data serial interface 2-wire serial bus the adg728/ADG729 are controlled via an i 2 c compat- ible serial bus. these parts are connected to this bus as a slave device (no clock is generated by the multiplexer) the adg728/ADG729 have different 7-bit slave ad- dresses. the five msbs of the adg728 are 10011, while the msbs of the ADG729 are 10001 and the two lsbs are determined by the state of the a0 and a1 pins. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition which is when a high to low transition on the sda line occurs while scl is high. the following byte is the address byte which consists of the 7-bit slave address followed by a r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master will read from the slave device. however, if the r/ w bit is low, the master will write to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowl- edge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3) when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low to high transition on the sda line while scl is high. in write mode, the master will pull the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the 9th clock pulse (i.e. the sda line remains high). the master will then bring the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition. see figure 3 below for a graphical explanation of the serial interface. a repeated write function gives the user flexibility to up- date the matrix switch a number of times after addressing the part only once. during the write cycle, each data byte will update the configuration of the switches. for exam- ple, after the matrix switch has acknowledged its address byte, and receives one data byte, the switches will update after the data byte, if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause an switch configuration up- date. repeat read of the matrix switch is also allowed. input shift register the input shift register is 8-bits wide. figure 2 illustrates the contents of the input shift register. data is loaded into the device as an 8-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 1. the 8-bit word consists of 8 data bits each controlling one switch. msb (bit 7) is loaded first. figure 2. adg728/ADG729 input shift register contents general description the adg728 and ADG729 are serially controlled, 8 channel and dual 4 channel matrix switches respectively. while providing the normal multiplexing and demultiplexing functions, these devices also provide the user with some more flexibility as to where their signal may be routed. each bit of the serial word corresponds to one switch of the device. a logic 1 in the particular bit position turns on the switch, while a logic 0 turns the switch off. because each switch is independently controlled by an individual bit, this provides the option of having any, all or none of the switches on. this feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together, (only seperated by the small on resistance of the switch). power on reset on power up of the device, all switches will be in the off condition and the internal shift register is filled with zeros and will remain so until a valid write takes place. s8 s7 s6 s5 s4 s3 s2 s1 db0 (lsb) db7 (msb) data bits
C8C rev. prc preliminary technical data preliminary technical data adg728/ADG729 write operation when writing to the adg728/ADG729, the user must begin with an address byte and r/ w bit, after which the switch will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the 8-bit word. the write operations for each matrix switch are shown in the figures below. figure 3. adg728 write sequence read operation when reading data back from the adg728/ADG729, the user must begin with an address byte and r/ w bit, after which the matrix switch will acknowledge that it is pre- pared to transmit data by pulling sda low. the readback operation is a single byte which consists of the 8 data bits in the input register. the read operations for each part are shown in the figures below. figure 5. adg728 readback sequence scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 11 a0r/w stop cond by master ack by adg728 start cond by master address byte data byte ack by adg728 a1 1 scl sda s8 s7 s6 s5 s4 s3 s2 s1 00 01 a0r/w stop cond by master ack by ADG729 start cond by master address byte data byte ack by ADG729 a1 1 figure 4. ADG729 write sequence scl sda s8 s7 s6 s5 s4 s3 s2 s1 1 0 0 1 1 a0 r/w stop cond by master ack by adg728 start cond by master address byte data byte no ack by master a1 scl sda s8 s7 s6 s5 s4 s3 s2 s1 0 0 0 1 a0 r/w stop cond by master ack by ADG729 start cond by master address byte data byte no ack by master a1 1 figure 6. ADG729 readback sequence
adg728/ADG729 C9C rev. prc preliminary technical data preliminary technical data test circuit 1. on resistance. test circuits test circuit 2. off leakage. test circuit 3. on leakage. test circuit 6. off isolation, bandwidth. test circuit 4. switching times. test circuit 5. charge injection. test circuit 7. crosstalk. i ds s r on = v 1 /i ds v1 v s d sd v s a a v d i d (off) i s (off) sd a v d i d (on) nc nc = not connected sd v s r l 300 w c l 35pf v out v dd 0.1f t on t off 90% 90% 50% 50% v in v out v dd gnd scl sda input register additional pins omitted for clarity s d v s gnd c l 1.0nf v out v dd r s v in v out d v out q inj = c l x d v out on off v dd scl sda input register s1 d r l 50 w gnd v out v dd 0.1f scl v dd network analyser v s 50 w sda crosstalk = 20 log vout/vs r l 50 w s1 d r l 50 w gnd v out v dd 0.1f scl v dd network analyser v s 50 w sda off isolation = 20 log v out /v s insertion loss = 20 log v out with switch/v s v out without switch/v s
adg728/ADG729 C10C rev .prc printed in u.s.a. 00000000 outline dimensions dimensions shown in inches and (mm). preliminary technical data preliminary technical data 16-lead tssop (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
|
